The purpose of a memory bus arbiter is to decide which of several memory users (referred to herein as ports) is to be allowed access to a bus and hence to memory connected to the bus. A generalized scenario is illustrated by FIG. 1. In FIG. 1, reference numeral 2 denotes a bus arbiter (labeled "bus arbitrator") for controlling accesses by a plurality of ports PORT.sub.0 . . . PORT.sub.15 to a memory bus 4. The memory bus 4 is connected to memory resource via an external memory interface not shown in FIG. 1. Alternatively, it could be connected directly to on-chip memory. Each port has a memory access path MA.sub.0 . . . MA.sub.15 connecting it to the memory bus by which memory addresses can be sent to the memory resource and items returned from the memory resource. Each port has a request line r.sub.0 . . . r.sub.15 connected to the bus arbiter and a grant line from the bus arbiter to each port g.sub.0 . . . g.sub.15. Each port also has a bus_busy line bb.sub.0 . . . bb.sub.15 connected through an OR gate 6 to the bus arbiter 2. Each port signals its request by asserting the request line r.sub.r . . . r.sub.15. Some time later the arbiter asserts one of the grant lines indicating which port can use the bus. This process is known as "awarding tenure" of the bus. On receipt of a grant signal a port asserts its bus_busy signal then uses the memory bus to satisfy one or more of its memory requests via its memory access path MA. When the port is finished it de-asserts the bus_busy signal allowing the arbiter to award tenure again.
A wide variety of arbitration schemes have been used in existing bus schemes. When a port has its request signal asserted it is referred to herein as a requester. The three most common are:
1) static priority--the arbiter defines a static rank ordering of each of the ports. It awards tenure to the requester with the highest rank. PA1 2) dynamic priority--similar to the static priority scheme insofar as the arbiter awards tenure to the requester with the highest rank, except that here following each granting the ranking is revised. The grantee is assigned lowest priority and the priority of all other ports which were below the grantee are increased by one. PA1 3) round robin--the arbiter defines a static ordering of the ports and maintains an indication of the last requester which was awarded tenure. In determining tenure, the arbiter starts at the port which follows the last port to have tenure, then awards tenure to the next requester it finds in its traversal order of the ports. The arbiter traversal order for round robin is to start at the lowest numbered port and visit successively numbered ports in turn until the last port is reached and then to wrap around and start traversing from the lowest number port again. PA1 a memory bus having an interface for accessing memory wherein items are held at locations in memory organized in address sets such that when one location in an address set has been accessed, remaining locations in the same address set can be accessed more quickly by a subsequent memory access than other locations in the memory; PA1 a plurality of memory users each having access to said memory bus and each operable to generate a request for access to the memory; PA1 an arbiter for controlling access to said memory bus by said memory users in response to said requests, PA1 wherein each memory user is operable to read the address of a current access to memory and to generate a same-address-set signal when the address of the last access by that memory user lies in the same set as the address of the current access, PA1 and wherein the arbiter holds for each memory user a predetermined number of accesses which are permitted by that memory user during an access span and, responsive to a request, grants up to that predetermined number of accesses provided that the same-address-set signal is asserted.
Some schemes are combinations of the above. It is often the case, in real-time applications, that access to memory needs to be shared in a manner such that there is a limit on the amount of time that a requester can be passed over for tenure regardless of the request behavior of other ports. This constraint severely limits the usefulness of many obvious arbitration schemes.